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* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
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* This source code is subject to NVIDIA ownership rights under U.S. and
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* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
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* U.S. Government End Users. This source code is a "commercial item" as
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* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
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* the above Disclaimer and U.S. Government End Users Notice.
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// (chosen as multiples of the thread block size for simplicity)
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#define WA (30 * BLOCK_SIZE) // Matrix A width
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#define HA (50 * BLOCK_SIZE) // Matrix A height
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#define WB (80 * BLOCK_SIZE) // Matrix B width
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#define HB WA // Matrix B height
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#define WC WB // Matrix C width
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#define HC HA // Matrix C height
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#endif // _MATRIXMUL_H_