/alps/ipecamera

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  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-27 00:28:57 UTC
  • Revision ID: csa@suren.me-20150427002857-82fk6r3e8rfgy4wr
First stand-alone ipecamera implementation

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model.c
 
1
#include <stdio.h>
 
2
 
 
3
#include <pcilib.h>
 
4
#include <pcilib/model.h>
 
5
 
 
6
#include "base.h"
 
7
#include "cmosis.h"
 
8
#include "model.h"
 
9
 
 
10
enum ipecamera_protocol_s {
 
11
    IPECAMERA_PROTOCOL_CMOSIS = PCILIB_REGISTER_PROTOCOL0,
 
12
};
 
13
 
 
14
 
 
15
static const pcilib_register_protocol_api_description_t ipecamera_cmosis_protocol_api =
 
16
    { NULL, NULL, ipecamera_cmosis_read, ipecamera_cmosis_write };
 
17
 
 
18
/*
 
19
static const pcilib_dma_description_t ipecamera_dma =
 
20
    { &ipe_dma_api, ipe_dma_banks, ipe_dma_registers, ipe_dma_engines, NULL, NULL, "ipedma", "DMA engine developed by M. Caselle" };
 
21
*/
 
22
 
 
23
static const pcilib_register_protocol_description_t ipecamera_protocols[] = {
 
24
//    {IPECAMERA_PROTOCOL_FPGA, &pcilib_default_protocol_api, "ipecamera", NULL, "cmosis", "Protocol to access FPGA registers"},
 
25
    {IPECAMERA_PROTOCOL_CMOSIS, &ipecamera_cmosis_protocol_api, NULL, NULL, "cmosis", "Protocol to access CMOSIS registers"},
 
26
    { 0 }
 
27
};
 
28
 
 
29
static const pcilib_register_bank_description_t ipecamera_banks[] = {
 
30
    { PCILIB_REGISTER_BANK0,    IPECAMERA_PROTOCOL_CMOSIS,              PCILIB_BAR0, IPECAMERA_CMOSIS_REGISTER_READ ,   IPECAMERA_CMOSIS_REGISTER_WRITE,         8,    128, PCILIB_LITTLE_ENDIAN, PCILIB_LITTLE_ENDIAN, "%lu"  , "cmosis", "CMOSIS CMV2000 Registers" },
 
31
    { PCILIB_REGISTER_BANK1,    PCILIB_REGISTER_PROTOCOL_DEFAULT,       PCILIB_BAR0, IPECAMERA_REGISTER_SPACE,          IPECAMERA_REGISTER_SPACE,               32, 0x0200, PCILIB_LITTLE_ENDIAN, PCILIB_LITTLE_ENDIAN, "0x%lx", "fpga", "IPECamera Registers" },
 
32
//    { PCILIB_REGISTER_BANK_DMA, PCILIB_REGISTER_PROTOCOL_DEFAULT,     PCILIB_BAR0, 0,                                 0,                                      32, 0x0200, PCILIB_LITTLE_ENDIAN, PCILIB_LITTLE_ENDIAN, "0x%lx", "dma", "DMA Registers"},
 
33
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
 
34
};
 
35
 
 
36
static const pcilib_register_description_t ipecamera_registers[] = {
 
37
{1,     0,      16,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines",  ""},
 
38
{3,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""},
 
39
{5,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""},
 
40
{7,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""},
 
41
{9,     0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""},
 
42
{11,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""},
 
43
{13,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""},
 
44
{15,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""},
 
45
{17,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""},
 
46
{19,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""},
 
47
{21,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""},
 
48
{23,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""},
 
49
{25,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""},
 
50
{27,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""},
 
51
{29,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""},
 
52
{31,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""},
 
53
{33,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""},
 
54
{35,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""},
 
55
{37,    0,      16,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""},
 
56
{39,    0,      1,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_color", ""},
 
57
{40,    0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""},
 
58
{41,    0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_flags", ""},
 
59
{42,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""},
 
60
{45,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step", ""},
 
61
{48,    0,      24,     1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp1", ""},
 
62
{51,    0,      24,     1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp2", ""},
 
63
{54,    0,      2,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""},
 
64
{55,    0,      8,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq", ""},
 
65
{56,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time2", ""},
 
66
{59,    0,      24,     1088,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step2", ""},
 
67
{68,    0,      2,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes2", ""},
 
68
{69,    0,      8,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq2", ""},
 
69
{70,    0,      16,     1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""},
 
70
{72,    0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""},
 
71
{78,    0,      12,     85,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""},
 
72
{80,    0,      18,     0x3FFFF,0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""},
 
73
{82,    0,      3,      7,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_82", ""},
 
74
{89,    0,      8,      96,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow2", ""},
 
75
{90,    0,      8,      96,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow3", ""},
 
76
{100,   0,      14,     16260,  0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""},
 
77
{102,   0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""},
 
78
{103,   0,      8,      32,     0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""},
 
79
{111,   0,      1,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_bit_mode", ""},
 
80
{112,   0,      2,      0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_resolution", ""},
 
81
{115,   0,      1,      1,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_115", ""},
 
82
{0x00,  0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
 
83
{0x10,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
 
84
{0x20,  0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
 
85
{0x30,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_info", ""},
 
86
{0x30,  0,      8,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_version",  ""},
 
87
{0x30,  8,      1,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_bitmode",  ""},
 
88
{0x30,  12,     2,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_resolution",  ""},
 
89
{0x30,  16,     2,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "output_mode",  ""},
 
90
{0x40,  0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "control", ""},
 
91
{0x50,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status", ""},
 
92
{0x54,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status2", ""},
 
93
{0x58,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""},
 
94
{0x5c,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_status", ""},
 
95
{0x70,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""},
 
96
{0x74,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""},
 
97
{0x78,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rd_address", ""},
 
98
{0xa0,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param1", ""},
 
99
{0xa0,  0,      10,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_skip_lines",  ""},
 
100
{0xa0,  10,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_num_lines",  ""},
 
101
{0xa0,  21,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_start_address",  ""},
 
102
{0xb0,  0,      32,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param2", ""},
 
103
{0xb0,  0,      11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_threshold_start_line",  ""},
 
104
{0xb0,  16,     10,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_area_lines",  ""},
 
105
{0xc0,  0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""},
 
106
{0xd0,  0,      32,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_thresholds", ""},
 
107
{0xd0,  0,      10,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_pixel_thr", ""},
 
108
{0xd0,  10,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_pixel_thr", ""},
 
109
{0xd0,  21,     11,     0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_lines_thr", ""},
 
110
{0x100, 0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""},
 
111
{0x110, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""},
 
112
{0x110, 0,      16,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature",  ""},
 
113
{0x110, 16,     3,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature_alarms",  ""},
 
114
{0x110, 19,     10,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature",  ""},
 
115
{0x110, 29,     3,      0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature_alarms",  ""},
 
116
{0x120, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_lines", ""},
 
117
{0x130, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_line", ""},
 
118
{0x140, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "exp_time", ""},
 
119
{0x150, 0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""},
 
120
{0x150, 0,      5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_phi",  ""},
 
121
{0x150, 5,      5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_z",  ""},
 
122
{0x150, 10,     5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_y",  ""},
 
123
{0x150, 15,     5,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_x",  ""},
 
124
{0x150, 20,     8,      0,      PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_gain",  ""},
 
125
{0x160, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""},
 
126
{0x170, 0,      32,     0,      0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""},
 
127
{0x180, 0,      32,     0x280,  0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""},
 
128
{0x190, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_period", ""},
 
129
{0x1a0, 0,      32,     0x64,   0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_max_frames", ""},
 
130
{0x1b0, 0,      32,     0,      0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_num_frames", ""},
 
131
{0,     0,      0,      0,      0,                        0,                  0,                        0,                     NULL, NULL}
 
132
};
 
133
 
 
134
static const pcilib_register_range_t ipecamera_ranges[] = {
 
135
//    {0xF000,  0xF000 + 128,   PCILIB_REGISTER_BANK0, 0},
 
136
//    {0x9000,  0x9FFF, PCILIB_REGISTER_BANK1, -0x9000},
 
137
    {0, 0, 0, 0}
 
138
};
 
139
 
 
140
static const pcilib_event_description_t ipecamera_events[] = {
 
141
    {PCILIB_EVENT0, "new_frame", ""},
 
142
    {0, NULL, NULL}
 
143
};
 
144
 
 
145
static const pcilib_event_data_type_description_t ipecamera_data_types[] = {
 
146
    {IPECAMERA_IMAGE_DATA,      PCILIB_EVENT0, "image", "16 bit pixel data" },
 
147
    {IPECAMERA_RAW_DATA,        PCILIB_EVENT0, "raw",   "raw data from camera" },
 
148
    {IPECAMERA_CHANGE_MASK,     PCILIB_EVENT0, "cmask", "change mask" },
 
149
    {0, 0, NULL, NULL}
 
150
};
 
151
 
 
152
pcilib_event_api_description_t ipecamera_image_api = {
 
153
    ipecamera_init,
 
154
    ipecamera_free,
 
155
 
 
156
    ipecamera_init_dma,
 
157
 
 
158
    ipecamera_reset,
 
159
    ipecamera_start,
 
160
    ipecamera_stop,
 
161
    ipecamera_trigger,
 
162
 
 
163
    ipecamera_stream,
 
164
    ipecamera_next_event,
 
165
    ipecamera_get,
 
166
    ipecamera_return
 
167
};
 
168
 
 
169
 
 
170
static const pcilib_model_description_t ipecamera_models[] = {{
 
171
    PCILIB_EVENT_INTERFACE_VERSION,
 
172
    &ipecamera_image_api,
 
173
    &pcilib_ipedma,
 
174
    ipecamera_registers,
 
175
    ipecamera_banks,
 
176
    ipecamera_protocols,
 
177
    ipecamera_ranges,
 
178
    ipecamera_events,
 
179
    ipecamera_data_types,
 
180
    "ipecamera",
 
181
    "IPE Camera"
 
182
}, { 0 }};
 
183
 
 
184
 
 
185
const pcilib_model_description_t *pcilib_get_event_model(pcilib_t *pcilib, unsigned short vendor_id, unsigned short device_id, const char *model) {
 
186
        // Enumeration call
 
187
    if ((!vendor_id)&&(!device_id)&&(!model)) {
 
188
        return ipecamera_models;
 
189
    }
 
190
 
 
191
    if ((vendor_id != 0x10ee)&&((!model)||(strcasecmp(model, "ipecamera"))))
 
192
        return NULL;
 
193
 
 
194
    return &ipecamera_models[0];
 
195
}