/alps/ipecamera

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Viewing changes to dma/nwl_irq.c

  • Committer: Suren A. Chilingaryan
  • Date: 2015-04-27 00:28:57 UTC
  • Revision ID: csa@suren.me-20150427002857-82fk6r3e8rfgy4wr
First stand-alone ipecamera implementation

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dma/nwl_irq.c
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/time.h>
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#include "pcilib.h"
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#include "pci.h"
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#include "error.h"
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#include "tools.h"
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#include "nwl_private.h"
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#include "nwl_defines.h"
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int dma_nwl_init_irq(nwl_dma_t *ctx, uint32_t val) {
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    if (val&(DMA_INT_ENABLE|DMA_USER_INT_ENABLE)) {
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        if (val&DMA_INT_ENABLE) ctx->irq_preserve |= PCILIB_DMA_IRQ;
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        if (val&DMA_USER_INT_ENABLE) ctx->irq_preserve |= PCILIB_EVENT_IRQ;
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    }
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    ctx->irq_started = 1;
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    return 0;
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}
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int dma_nwl_free_irq(nwl_dma_t *ctx) {
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    if (ctx->irq_started) {
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        dma_nwl_disable_irq((pcilib_dma_context_t*)ctx, 0);
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        if (ctx->irq_preserve) dma_nwl_enable_irq((pcilib_dma_context_t*)ctx, ctx->irq_preserve, 0);
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        ctx->irq_enabled = 0;
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        ctx->irq_started = 0;
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    }
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    return 0;
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}
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int dma_nwl_enable_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t type, pcilib_dma_flags_t flags) {
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    uint32_t val;
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    if (flags&PCILIB_DMA_FLAG_PERSISTENT) ctx->irq_preserve |= type;
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    if ((ctx->irq_enabled&type) == type) return 0;
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    type |= ctx->irq_enabled;
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    nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    if (!ctx->irq_started) dma_nwl_init_irq(ctx, val);
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    val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    pcilib_clear_irq(ctx->pcilib, NWL_DMA_IRQ_SOURCE);
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    if (type & PCILIB_DMA_IRQ) val |= DMA_INT_ENABLE;
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    if (type & PCILIB_EVENT_IRQ) val |= DMA_USER_INT_ENABLE;
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    nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    ctx->irq_enabled = type;
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    return 0;
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}
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int dma_nwl_disable_irq(pcilib_dma_context_t *vctx, pcilib_dma_flags_t flags) {
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    uint32_t val;
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    ctx->irq_enabled = 0;
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    nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    if (!ctx->irq_started) dma_nwl_init_irq(ctx, val);
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    val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS);
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    if (flags&PCILIB_DMA_FLAG_PERSISTENT) ctx->irq_preserve = 0;
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    return 0;
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}
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int dma_nwl_enable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma) {
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    uint32_t val;
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    dma_nwl_enable_irq((pcilib_dma_context_t*)ctx, PCILIB_DMA_IRQ, 0);
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    nwl_read_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS);
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    val |= (DMA_ENG_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS);
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    return 0;
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}
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int dma_nwl_disable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma) {
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    uint32_t val;
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    nwl_read_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS);
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    val &= ~(DMA_ENG_INT_ENABLE);
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    nwl_write_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS);
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    return 0;
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}
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int dma_nwl_acknowledge_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t irq_type, pcilib_irq_source_t irq_source) {
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    uint32_t val;
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    nwl_dma_t *ctx = (nwl_dma_t*)vctx;
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    pcilib_nwl_engine_description_t *info = ctx->engines + irq_source;
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    if (irq_type != PCILIB_DMA_IRQ) return PCILIB_ERROR_NOTSUPPORTED;
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    if (irq_source >= ctx->n_engines) return PCILIB_ERROR_NOTAVAILABLE;
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    nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);
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    if (val & DMA_ENG_INT_ACTIVE_MASK) {
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        val |= DMA_ENG_ALLINT_MASK;
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        nwl_write_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS);
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    }
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    return 0;
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}