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  • Committer: Suren A. Chilingaryan
  • Date: 2011-03-08 21:46:14 UTC
  • mto: This revision was merged to the branch mainline in revision 8.
  • Revision ID: csa@dside.dyndns.org-20110308214614-g5v841m61jilcrm2
Initial support of IPECamera protocol

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#include "pci.h"
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#define IPECAMERA_REGISTER_SPACE 0xfeaffc00
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#define IPECAMERA_REGISTER_WRITE (IPECAMERA_REGISTER_SPACE)
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#define IPECAMERA_REGISTER_READ (IPECAMERA_REGISTER_SPACE + 4)
 
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#define IPECAMERA_REGISTER_WRITE (IPECAMERA_REGISTER_SPACE + 0)
 
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#define IPECAMERA_REGISTER_READ (IPECAMERA_REGISTER_WRITE + 4)
 
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#ifdef _IPECAMERA_C
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pcilib_register_t ipecamera_registers[] = {
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{1,     16,     1088,   PCILIB_REGISTER_RW, "number_lines", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{3,     16,     0,      PCILIB_REGISTER_RW, "start1", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{5,     16,     0,      PCILIB_REGISTER_RW, "start2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{7,     16,     0,      PCILIB_REGISTER_RW, "start3", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{9,     16,     0,      PCILIB_REGISTER_RW, "start4", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{11,    16,     0,      PCILIB_REGISTER_RW, "start5", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{13,    16,     0,      PCILIB_REGISTER_RW, "start6", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{15,    16,     0,      PCILIB_REGISTER_RW, "start7", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{17,    16,     0,      PCILIB_REGISTER_RW, "start8", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{19,    16,     0,      PCILIB_REGISTER_RW, "number_lines1", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{21,    16,     0,      PCILIB_REGISTER_RW, "number_lines2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{23,    16,     0,      PCILIB_REGISTER_RW, "number_lines3", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{25,    16,     0,      PCILIB_REGISTER_RW, "number_lines4", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{27,    16,     0,      PCILIB_REGISTER_RW, "number_lines5", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{29,    16,     0,      PCILIB_REGISTER_RW, "number_lines6", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{31,    16,     0,      PCILIB_REGISTER_RW, "number_lines7", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{33,    16,     0,      PCILIB_REGISTER_RW, "number_lines8", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{35,    16,     0,      PCILIB_REGISTER_RW, "sub_s", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{37,    16,     0,      PCILIB_REGISTER_RW, "sub_a", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{39,    1,      1,      PCILIB_REGISTER_RW, "color", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{40,    2,      0,      PCILIB_REGISTER_RW, "image_flipping", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{41,    2,      0,      PCILIB_REGISTER_RW, "exp_flags", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{42,    24,     1088,   PCILIB_REGISTER_RW, "exp_time", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{45,    24,     1088,   PCILIB_REGISTER_RW, "exp_step", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{48,    24,     1,      PCILIB_REGISTER_RW, "exp_kp1", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{51,    24,     1,      PCILIB_REGISTER_RW, "exp_kp2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{54,    2,      1,      PCILIB_REGISTER_RW, "nr_slopes", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{55,    8,      1,      PCILIB_REGISTER_RW, "exp_seq", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{56,    24,     1088,   PCILIB_REGISTER_RW, "exp_time2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{59,    24,     1088,   PCILIB_REGISTER_RW, "exp_step2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{68,    2,      1,      PCILIB_REGISTER_RW, "nr_slopes2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{69,    8,      1,      PCILIB_REGISTER_RW, "exp_seq2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{70,    16,     1,      PCILIB_REGISTER_RW, "number_frames", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{72,    2,      0,      PCILIB_REGISTER_RW, "output_mode", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{78,    12,     85,     PCILIB_REGISTER_RW, "training_pattern", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{80,    18,     0x3FFFF,PCILIB_REGISTER_RW, "channel_en", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{89,    8,      96,     PCILIB_REGISTER_RW, "vlow2", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{90,    8,      96,     PCILIB_REGISTER_RW, "vlow3", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{100,   14,     16260,  PCILIB_REGISTER_RW, "offset", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{102,   2,      0,      PCILIB_REGISTER_RW, "pga", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{103,   8,      32,     PCILIB_REGISTER_RW, "adc_gain", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{111,   1,      1,      PCILIB_REGISTER_RW, "bit_mode", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{112,   2,      0,      PCILIB_REGISTER_RW, "adc_resolution", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{126,   16,     0,      PCILIB_REGISTER_RW, "temp", IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, ""},
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{0,     0,      0,      0, NULL, 0, 0, 0, NULL}
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};
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pcilib_register_range_t ipecamera_register_range[] = {
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    {0, 128}, {0,0}
 
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pcilib_register_bank_description_t ipecamera_register_banks[] = {
 
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    { PCILIB_REGISTER_BANK0, IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE,  PCILIB_BIG_ENDIAN, 8, PCILIB_LITTLE_ENDIAN },
 
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    { 0, 0, 0, 0, 0 }
 
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};
 
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pcilib_register_description_t ipecamera_registers[] = {
 
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{1,     16,     1088,   PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines",  ""},
 
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{3,     16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start1", ""},
 
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{5,     16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start2", ""},
 
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{7,     16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start3", ""},
 
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{9,     16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start4", ""},
 
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{11,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start5", ""},
 
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{13,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start6", ""},
 
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{15,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start7", ""},
 
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{17,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "start8", ""},
 
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{19,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines1", ""},
 
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{21,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines2", ""},
 
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{23,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines3", ""},
 
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{25,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines4", ""},
 
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{27,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines5", ""},
 
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{29,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines6", ""},
 
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{31,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines7", ""},
 
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{33,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_lines8", ""},
 
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{35,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "sub_s", ""},
 
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{37,    16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "sub_a", ""},
 
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{39,    1,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "color", ""},
 
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{40,    2,      0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "image_flipping", ""},
 
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{41,    2,      0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_flags", ""},
 
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{42,    24,     1088,   PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_time", ""},
 
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{45,    24,     1088,   PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_step", ""},
 
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{48,    24,     1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_kp1", ""},
 
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{51,    24,     1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_kp2", ""},
 
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{54,    2,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "nr_slopes", ""},
 
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{55,    8,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_seq", ""},
 
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{56,    24,     1088,   PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_time2", ""},
 
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{59,    24,     1088,   PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_step2", ""},
 
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{68,    2,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "nr_slopes2", ""},
 
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{69,    8,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "exp_seq2", ""},
 
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{70,    16,     1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "number_frames", ""},
 
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{72,    2,      0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "output_mode", ""},
 
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{78,    12,     85,     PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "training_pattern", ""},
 
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{80,    18,     0x3FFFF,PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "channel_en", ""},
 
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{89,    8,      96,     PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "vlow2", ""},
 
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{90,    8,      96,     PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "vlow3", ""},
 
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{100,   14,     16260,  PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "offset", ""},
 
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{102,   2,      0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "pga", ""},
 
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{103,   8,      32,     PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "adc_gain", ""},
 
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{111,   1,      1,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "bit_mode", ""},
 
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{112,   2,      0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "adc_resolution", ""},
 
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{126,   16,     0,      PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "temp", ""},
 
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{0,     0,      0,      0,                  0,                     NULL, NULL}
 
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};
 
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pcilib_register_range_t ipecamera_register_ranges[] = {
 
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    {0, 128, PCILIB_REGISTER_BANK0}, {0, 0, 0}
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};
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#else
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extern pcilib_register_t ipecamera_registers[];
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extern pcilib_register_range_t ipecamera_register_range[];
 
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extern pcilib_register_description_t ipecamera_registers[];
 
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extern pcilib_register_bank_description_t ipecamera_register_banks[];
 
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extern pcilib_register_range_t ipecamera_register_ranges[];
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#endif 
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int ipecamera_read(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_addr_t addr, uint8_t bits, pcilib_register_value_t *value);
 
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int ipecamera_write(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcilib_register_addr_t addr, uint8_t bits, pcilib_register_value_t value);
 
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#endif /* _IPECAMERA_H */