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  • Committer: Suren A. Chilingaryan
  • Date: 2015-11-20 05:04:08 UTC
  • Revision ID: csa@suren.me-20151120050408-jrzier07533vly8f
Support large DMA pages in IPEDMA

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Lines of Context:
dma/ipe.c
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    if (ctx->pages) return 0;
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#ifdef IPEDMA_TLP_SIZE  
 
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        tlp_size = IPEDMA_TLP_SIZE;
 
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#else /* IPEDMA_TLP_SIZE */
 
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        link_info = pcilib_get_pcie_link_info(vctx->pcilib);
 
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        if (link_info) {
 
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            tlp_size = 1<<link_info->payload;
 
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            if (tlp_size > IPEDMA_MAX_TLP_SIZE)
 
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                tlp_size = IPEDMA_MAX_TLP_SIZE;
 
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        } else tlp_size = 128;
 
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#endif /* IPEDMA_TLP_SIZE */
 
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    if (!pcilib_read_register(ctx->dmactx.pcilib, "dmaconf", "dma_timeout", &value))
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        ctx->dma_timeout = value;
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    else 
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        ctx->dma_timeout = IPEDMA_DMA_TIMEOUT;
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    if (!pcilib_read_register(ctx->dmactx.pcilib, "dmaconf", "dma_page_size", &value))
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        ctx->dma_page_size = value;
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    else
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        ctx->dma_page_size = IPEDMA_PAGE_SIZE;
 
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    if (!pcilib_read_register(ctx->dmactx.pcilib, "dmaconf", "dma_page_size", &value)) {
 
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        if (value % IPEDMA_PAGE_SIZE) {
 
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            pcilib_error("Invalid DMA page size (%lu) is configured", value);
 
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            return PCILIB_ERROR_INVALID_ARGUMENT;
 
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        }
 
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        //if ((value)&&((value / (tlp_size * IPEDMA_CORES)) > ...seems no limit...)) { ... fail ... }
 
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        ctx->page_size = value;
 
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    } else
 
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        ctx->page_size = IPEDMA_PAGE_SIZE;
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    if (!pcilib_read_register(ctx->dmactx.pcilib, "dmaconf", "dma_pages", &value))
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        ctx->dma_pages = value;
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    kflags = PCILIB_KMEM_FLAG_REUSE|PCILIB_KMEM_FLAG_EXCLUSIVE|PCILIB_KMEM_FLAG_HARDWARE|(ctx->preserve?PCILIB_KMEM_FLAG_PERSISTENT:0);
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    pcilib_kmem_handle_t *desc = pcilib_alloc_kernel_memory(ctx->dmactx.pcilib, PCILIB_KMEM_TYPE_CONSISTENT, 1, IPEDMA_DESCRIPTOR_SIZE, IPEDMA_DESCRIPTOR_ALIGNMENT, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_RING, 0x00), kflags);
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    pcilib_kmem_handle_t *pages = pcilib_alloc_kernel_memory(ctx->dmactx.pcilib, PCILIB_KMEM_TYPE_DMA_C2S_PAGE, IPEDMA_DMA_PAGES, 0, 0, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_PAGES, 0x00), kflags);
 
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    pcilib_kmem_handle_t *pages = pcilib_alloc_kernel_memory(ctx->dmactx.pcilib, PCILIB_KMEM_TYPE_DMA_C2S_PAGE, IPEDMA_DMA_PAGES, ctx->page_size, 0, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_PAGES, 0x00), kflags);
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    if (!desc||!pages) {
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        if (pages) pcilib_free_kernel_memory(ctx->dmactx.pcilib, pages, 0);
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        last_written_addr_ptr = desc_va + 2 * sizeof(uint32_t);
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    }
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        // get page size if default size was used
 
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    if (!ctx->page_size) {
 
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        ctx->page_size = pcilib_kmem_get_block_size(ctx->dmactx.pcilib, pages, 0);
 
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    }
 
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    if (preserve) {
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        ctx->reused = 1;
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        ctx->preserve = 1;
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        if (ctx->mode64) address64 = 0x8000 | (0<<24);
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        else address64 = 0;
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#ifdef IPEDMA_TLP_SIZE  
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        tlp_size = IPEDMA_TLP_SIZE;
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#else /* IPEDMA_TLP_SIZE */
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        link_info = pcilib_get_pcie_link_info(vctx->pcilib);
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        if (link_info) {
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            tlp_size = 1<<link_info->payload;
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            if (tlp_size > IPEDMA_MAX_TLP_SIZE)
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                tlp_size = IPEDMA_MAX_TLP_SIZE;
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        } else tlp_size = 128;
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#endif /* IPEDMA_TLP_SIZE */
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        WR(IPEDMA_REG_TLP_SIZE,  address64 | (tlp_size>>2));
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        WR(IPEDMA_REG_TLP_COUNT, IPEDMA_PAGE_SIZE / (tlp_size * IPEDMA_CORES));
 
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        WR(IPEDMA_REG_TLP_COUNT, ctx->page_size / (tlp_size * IPEDMA_CORES));
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            // Setting progress register threshold
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        WR(IPEDMA_REG_UPDATE_THRESHOLD, IPEDMA_DMA_PROGRESS_THRESHOLD);
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    ctx->desc = desc;
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    ctx->pages = pages;
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    ctx->page_size = pcilib_kmem_get_block_size(ctx->dmactx.pcilib, pages, 0);
 
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    ctx->ring_size = IPEDMA_DMA_PAGES;
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    return 0;