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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-02-03 16:09:46 +0100 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-02-03 16:09:46 +0100 |
| commit | 9471f1ff77cf1c85f83726ba7d39bbb59a09496a (patch) | |
| tree | 1e7f6b5864886bc761b51bf3ae594b1cdb6a7a54 /dma | |
| parent | c1df150330d0675da6a373954a4f3634be947048 (diff) | |
| download | pcitool-9471f1ff77cf1c85f83726ba7d39bbb59a09496a.tar.gz pcitool-9471f1ff77cf1c85f83726ba7d39bbb59a09496a.tar.bz2 pcitool-9471f1ff77cf1c85f83726ba7d39bbb59a09496a.tar.xz pcitool-9471f1ff77cf1c85f83726ba7d39bbb59a09496a.zip | |
Support 64 bit mode, but disable due to problems in hardware
Diffstat (limited to 'dma')
| -rw-r--r-- | dma/ipe.c | 11 |
1 files changed, 9 insertions, 2 deletions
@@ -32,6 +32,7 @@ pcilib_dma_context_t *dma_ipe_init(pcilib_t *pcilib, pcilib_dma_modification_t t if (ctx) { memset(ctx, 0, sizeof(ipe_dma_t)); ctx->pcilib = pcilib; +// ctx->mode64 = 1; memset(ctx->engine, 0, 2 * sizeof(pcilib_dma_engine_description_t)); ctx->engine[0].addr = 0; @@ -85,6 +86,9 @@ int dma_ipe_start(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dm volatile uint32_t *last_written_addr_ptr; pcilib_register_value_t value, value2; + + uint32_t address64; + if (dma == PCILIB_DMA_ENGINE_INVALID) return 0; else if (dma > 1) return PCILIB_ERROR_INVALID_BANK; @@ -167,8 +171,11 @@ int dma_ipe_start(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dm if (value != 0x14031700) pcilib_warning("PCIe is not ready, code is %lx", value); #endif /* IPEDMA_BUG_DMARD */ - // Configuring TLP and PACKET sizes (40 bit mode can be used with big pre-allocated buffers later) - WR(IPEDMA_REG_TLP_SIZE, IPEDMA_TLP_SIZE); + // Enable 64 bit addressing and configure TLP and PACKET sizes (40 bit mode can be used with big pre-allocated buffers later) + if (ctx->mode64) address64 = 0x8000 | (0<<24); + else address64 = 0; + + WR(IPEDMA_REG_TLP_SIZE, address64 | IPEDMA_TLP_SIZE); WR(IPEDMA_REG_TLP_COUNT, IPEDMA_PAGE_SIZE / (4 * IPEDMA_TLP_SIZE * IPEDMA_CORES)); // Setting progress register threshold |