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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-04-20 22:01:04 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-04-20 22:01:04 +0200 |
| commit | 77c4d6e67debf0e729734d882df033c4c0f5b0c3 (patch) | |
| tree | 4a59e86332d6cc78fc5c97110ecba281b0f67bc9 /dma/nwl_irq.c | |
| parent | 0002c0cc260a6a8e2b6c53f19ae99a625eca4355 (diff) | |
| download | pcitool-77c4d6e67debf0e729734d882df033c4c0f5b0c3.tar.gz pcitool-77c4d6e67debf0e729734d882df033c4c0f5b0c3.tar.bz2 pcitool-77c4d6e67debf0e729734d882df033c4c0f5b0c3.tar.xz pcitool-77c4d6e67debf0e729734d882df033c4c0f5b0c3.zip | |
Big redign of model structures
Diffstat (limited to 'dma/nwl_irq.c')
| -rw-r--r-- | dma/nwl_irq.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/dma/nwl_irq.c b/dma/nwl_irq.c index e71c76a..cbc087b 100644 --- a/dma/nwl_irq.c +++ b/dma/nwl_irq.c @@ -49,7 +49,7 @@ int dma_nwl_enable_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t type, pcili val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE); nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS); - pcilib_clear_irq(ctx->pcilib, NWL_DMA_IRQ_SOURCE); + pcilib_clear_irq(ctx->dmactx.pcilib, NWL_DMA_IRQ_SOURCE); if (type & PCILIB_DMA_IRQ) val |= DMA_INT_ENABLE; if (type & PCILIB_EVENT_IRQ) val |= DMA_USER_INT_ENABLE; @@ -104,15 +104,15 @@ int dma_nwl_acknowledge_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t irq_ty uint32_t val; nwl_dma_t *ctx = (nwl_dma_t*)vctx; - pcilib_nwl_engine_description_t *info = ctx->engines + irq_source; + pcilib_nwl_engine_context_t *ectx = ctx->engines + irq_source; if (irq_type != PCILIB_DMA_IRQ) return PCILIB_ERROR_NOTSUPPORTED; - if (irq_source >= ctx->n_engines) return PCILIB_ERROR_NOTAVAILABLE; + if (irq_source >= ctx->dmactx.pcilib->num_engines) return PCILIB_ERROR_NOTAVAILABLE; - nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); + nwl_read_register(val, ctx, ectx->base_addr, REG_DMA_ENG_CTRL_STATUS); if (val & DMA_ENG_INT_ACTIVE_MASK) { val |= DMA_ENG_ALLINT_MASK; - nwl_write_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); + nwl_write_register(val, ctx, ectx->base_addr, REG_DMA_ENG_CTRL_STATUS); } return 0; |