\begin{algorithm}[htb]
\DontPrintSemicolon
\caption{\label{alg:cache64} The caching stage of \algorithmname~\ref{alg:alurec} optimized for architectures with 64-bit shared memory}
\ForTo{i}{0}{s_i}{
    $h \eq 2 \mul (i \mul s_t + m_d) $ \;
    $d_1 \eq $ \KwTex{$h_m + h + \fconst{0.5}$, $p + \fconst{0.5}$} \;
    $d_2 \eq $ \KwTex{$h_m + h + \fconst{1.5}$, $p + \fconst{0.5}$} \;
    $\cast{float2}{\shmem{\vfloat{d}}[m_p][h]} = (float2)\vlist{d_1,d_2}$ \;
}
\end{algorithm} 