bzr branch
http://darksoft.org/webbzr/alps/ipecamera
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
1 |
#include <stdio.h> |
2 |
||
3 |
#include <pcilib.h> |
|
4 |
#include <pcilib/model.h> |
|
5 |
||
6 |
#include "base.h" |
|
7 |
#include "cmosis.h" |
|
8 |
#include "model.h" |
|
|
253
by Suren A. Chilingaryan
Provide version information as required by new pcilib interface |
9 |
#include "version.h" |
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
10 |
|
11 |
enum ipecamera_protocol_s { |
|
12 |
IPECAMERA_PROTOCOL_CMOSIS = PCILIB_REGISTER_PROTOCOL0, |
|
13 |
};
|
|
14 |
||
15 |
||
16 |
static const pcilib_register_protocol_api_description_t ipecamera_cmosis_protocol_api = |
|
|
264
by Suren A. Chilingaryan
Serialize access to CMOSIS registers |
17 |
{ IPECAMERA_VERSION, ipecamera_cmosis_open, ipecamera_cmosis_close, ipecamera_cmosis_read, ipecamera_cmosis_write }; |
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
18 |
|
19 |
/*
|
|
20 |
static const pcilib_dma_description_t ipecamera_dma =
|
|
21 |
{ &ipe_dma_api, ipe_dma_banks, ipe_dma_registers, ipe_dma_engines, NULL, NULL, "ipedma", "DMA engine developed by M. Caselle" };
|
|
22 |
*/
|
|
23 |
||
24 |
static const pcilib_register_protocol_description_t ipecamera_protocols[] = { |
|
25 |
// {IPECAMERA_PROTOCOL_FPGA, &pcilib_default_protocol_api, "ipecamera", NULL, "cmosis", "Protocol to access FPGA registers"},
|
|
26 |
{IPECAMERA_PROTOCOL_CMOSIS, &ipecamera_cmosis_protocol_api, NULL, NULL, "cmosis", "Protocol to access CMOSIS registers"}, |
|
27 |
{ 0 } |
|
28 |
};
|
|
29 |
||
30 |
static const pcilib_register_bank_description_t ipecamera_banks[] = { |
|
31 |
{ PCILIB_REGISTER_BANK0, IPECAMERA_PROTOCOL_CMOSIS, PCILIB_BAR0, IPECAMERA_CMOSIS_REGISTER_READ , IPECAMERA_CMOSIS_REGISTER_WRITE, 8, 128, PCILIB_LITTLE_ENDIAN, PCILIB_LITTLE_ENDIAN, "%lu" , "cmosis", "CMOSIS CMV2000 Registers" }, |
|
32 |
{ PCILIB_REGISTER_BANK1, PCILIB_REGISTER_PROTOCOL_DEFAULT, PCILIB_BAR0, IPECAMERA_REGISTER_SPACE, IPECAMERA_REGISTER_SPACE, 32, 0x0200, PCILIB_LITTLE_ENDIAN, PCILIB_LITTLE_ENDIAN, "0x%lx", "fpga", "IPECamera Registers" }, |
|
33 |
// { PCILIB_REGISTER_BANK_DMA, PCILIB_REGISTER_PROTOCOL_DEFAULT, PCILIB_BAR0, 0, 0, 32, 0x0200, PCILIB_LITTLE_ENDIAN, PCILIB_LITTLE_ENDIAN, "0x%lx", "dma", "DMA Registers"},
|
|
34 |
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL } |
|
35 |
};
|
|
36 |
||
|
260
by Suren A. Chilingaryan
Support registers of CMOSIS20000 camera |
37 |
|
38 |
const pcilib_register_description_t cmosis_registers[] = { |
|
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
39 |
{1, 0, 16, 1088, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines", ""}, |
40 |
{3, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""}, |
|
41 |
{5, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""}, |
|
42 |
{7, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""}, |
|
43 |
{9, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""}, |
|
44 |
{11, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""}, |
|
45 |
{13, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""}, |
|
46 |
{15, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""}, |
|
47 |
{17, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""}, |
|
48 |
{19, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""}, |
|
49 |
{21, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""}, |
|
50 |
{23, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""}, |
|
51 |
{25, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""}, |
|
52 |
{27, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""}, |
|
53 |
{29, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""}, |
|
54 |
{31, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""}, |
|
55 |
{33, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""}, |
|
56 |
{35, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""}, |
|
57 |
{37, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""}, |
|
58 |
{39, 0, 1, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_color", ""}, |
|
59 |
{40, 0, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""}, |
|
60 |
{41, 0, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_flags", ""}, |
|
61 |
{42, 0, 24, 1088, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""}, |
|
62 |
{45, 0, 24, 1088, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step", ""}, |
|
63 |
{48, 0, 24, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp1", ""}, |
|
64 |
{51, 0, 24, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp2", ""}, |
|
65 |
{54, 0, 2, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""}, |
|
66 |
{55, 0, 8, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq", ""}, |
|
67 |
{56, 0, 24, 1088, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time2", ""}, |
|
68 |
{59, 0, 24, 1088, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step2", ""}, |
|
69 |
{68, 0, 2, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes2", ""}, |
|
70 |
{69, 0, 8, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq2", ""}, |
|
71 |
{70, 0, 16, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""}, |
|
72 |
{72, 0, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""}, |
|
73 |
{78, 0, 12, 85, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""}, |
|
74 |
{80, 0, 18, 0x3FFFF,0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""}, |
|
75 |
{82, 0, 3, 7, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_82", ""}, |
|
76 |
{89, 0, 8, 96, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow2", ""}, |
|
77 |
{90, 0, 8, 96, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow3", ""}, |
|
78 |
{100, 0, 14, 16260, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""}, |
|
79 |
{102, 0, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""}, |
|
80 |
{103, 0, 8, 32, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""}, |
|
81 |
{111, 0, 1, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_bit_mode", ""}, |
|
82 |
{112, 0, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_resolution", ""}, |
|
83 |
{115, 0, 1, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_115", ""}, |
|
|
260
by Suren A. Chilingaryan
Support registers of CMOSIS20000 camera |
84 |
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} |
85 |
};
|
|
86 |
||
87 |
const pcilib_register_description_t cmosis20000_registers[] = { |
|
88 |
{15, 0, 2, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""}, |
|
89 |
{22, 0, 16, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""}, |
|
90 |
{24, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start_single", ""}, |
|
91 |
{26, 0, 16, 3840, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines_single", ""}, |
|
92 |
{28, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""}, |
|
93 |
{30, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""}, |
|
94 |
{32, 0, 16, 3840, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""}, |
|
95 |
{37, 0, 2, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""}, |
|
96 |
{39, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_s2", ""}, |
|
97 |
{42, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_s3", ""}, |
|
98 |
{44, 0, 1, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_multwin_en", ""}, |
|
99 |
{45, 0, 16, 3840, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines", ""}, |
|
100 |
{47, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""}, |
|
101 |
{49, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""}, |
|
102 |
{51, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""}, |
|
103 |
{53, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""}, |
|
104 |
{55, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""}, |
|
105 |
{57, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""}, |
|
106 |
{59, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""}, |
|
107 |
{61, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""}, |
|
108 |
{63, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""}, |
|
109 |
{65, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""}, |
|
110 |
{67, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""}, |
|
111 |
{69, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""}, |
|
112 |
{71, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""}, |
|
113 |
{73, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""}, |
|
114 |
{75, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""}, |
|
115 |
{77, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""}, |
|
116 |
{80, 0, 1, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""}, |
|
117 |
{81, 0, 1, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_ext", ""}, |
|
118 |
{82, 0, 8, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_fot_mult", ""}, |
|
119 |
{83, 0, 1, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_testpattern_en", ""}, |
|
120 |
{85, 0, 1, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""}, |
|
121 |
{88, 0, 15, 2840, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""}, |
|
122 |
{90, 0, 16, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""}, |
|
123 |
{93, 2, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""}, |
|
124 |
{95, 0, 19, 0x7FFFF,0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""}, |
|
125 |
{101, 0, 16, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_temp", ""}, |
|
126 |
{112, 0, 7, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlevel_s2_ex", ""}, |
|
127 |
{113, 0, 7, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlevel_s3_ex", ""}, |
|
128 |
{114, 0, 7, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlevel_s2", ""}, |
|
129 |
{115, 0, 7, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlevel_s3", ""}, |
|
130 |
{103, 0, 6, 32, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""}, |
|
131 |
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} |
|
132 |
};
|
|
133 |
||
134 |
static const pcilib_register_description_t ipecamera_registers[] = { |
|
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
135 |
{0x00, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""}, |
136 |
{0x10, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""}, |
|
137 |
{0x20, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""}, |
|
138 |
{0x30, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_info", ""}, |
|
139 |
{0x30, 0, 8, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "firmware_version", ""}, |
|
140 |
{0x30, 8, 1, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "firmware_bitmode", ""}, |
|
141 |
{0x30, 12, 2, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "adc_resolution", ""}, |
|
142 |
{0x30, 16, 2, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "output_mode", ""}, |
|
143 |
{0x40, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "control", ""}, |
|
144 |
{0x50, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status", ""}, |
|
145 |
{0x54, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status2", ""}, |
|
146 |
{0x58, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""}, |
|
147 |
{0x5c, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_status", ""}, |
|
148 |
{0x70, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""}, |
|
149 |
{0x74, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""}, |
|
150 |
{0x78, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rd_address", ""}, |
|
151 |
{0xa0, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param1", ""}, |
|
152 |
{0xa0, 0, 10, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_skip_lines", ""}, |
|
153 |
{0xa0, 10, 11, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_num_lines", ""}, |
|
154 |
{0xa0, 21, 11, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_start_address", ""}, |
|
155 |
{0xb0, 0, 32, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param2", ""}, |
|
156 |
{0xb0, 0, 11, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_threshold_start_line", ""}, |
|
157 |
{0xb0, 16, 10, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_area_lines", ""}, |
|
158 |
{0xc0, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""}, |
|
159 |
{0xd0, 0, 32, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_thresholds", ""}, |
|
160 |
{0xd0, 0, 10, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_pixel_thr", ""}, |
|
161 |
{0xd0, 10, 11, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_pixel_thr", ""}, |
|
162 |
{0xd0, 21, 11, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_lines_thr", ""}, |
|
163 |
{0x100, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""}, |
|
164 |
{0x110, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""}, |
|
165 |
{0x110, 0, 16, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "sensor_temperature", ""}, |
|
166 |
{0x110, 16, 3, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "sensor_temperature_alarms", ""}, |
|
167 |
{0x110, 19, 10, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fpga_temperature", ""}, |
|
168 |
{0x110, 29, 3, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fpga_temperature_alarms", ""}, |
|
169 |
{0x120, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_lines", ""}, |
|
170 |
{0x130, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_line", ""}, |
|
171 |
{0x140, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "exp_time", ""}, |
|
172 |
{0x150, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""}, |
|
173 |
{0x150, 0, 5, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_phi", ""}, |
|
174 |
{0x150, 5, 5, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_z", ""}, |
|
175 |
{0x150, 10, 5, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_y", ""}, |
|
176 |
{0x150, 15, 5, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_x", ""}, |
|
177 |
{0x150, 20, 8, 0, PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "adc_gain", ""}, |
|
178 |
{0x160, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""}, |
|
179 |
{0x170, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""}, |
|
180 |
{0x180, 0, 32, 0x280, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""}, |
|
181 |
{0x190, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_period", ""}, |
|
182 |
{0x1a0, 0, 32, 0x64, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_max_frames", ""}, |
|
183 |
{0x1b0, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_num_frames", ""}, |
|
184 |
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} |
|
185 |
};
|
|
186 |
||
187 |
static const pcilib_register_range_t ipecamera_ranges[] = { |
|
188 |
// {0xF000, 0xF000 + 128, PCILIB_REGISTER_BANK0, 0},
|
|
189 |
// {0x9000, 0x9FFF, PCILIB_REGISTER_BANK1, -0x9000},
|
|
190 |
{0, 0, 0, 0} |
|
191 |
};
|
|
192 |
||
193 |
static const pcilib_event_description_t ipecamera_events[] = { |
|
194 |
{PCILIB_EVENT0, "new_frame", ""}, |
|
195 |
{0, NULL, NULL} |
|
196 |
};
|
|
197 |
||
198 |
static const pcilib_event_data_type_description_t ipecamera_data_types[] = { |
|
199 |
{IPECAMERA_IMAGE_DATA, PCILIB_EVENT0, "image", "16 bit pixel data" }, |
|
200 |
{IPECAMERA_RAW_DATA, PCILIB_EVENT0, "raw", "raw data from camera" }, |
|
201 |
{IPECAMERA_CHANGE_MASK, PCILIB_EVENT0, "cmask", "change mask" }, |
|
202 |
{0, 0, NULL, NULL} |
|
203 |
};
|
|
204 |
||
205 |
pcilib_event_api_description_t ipecamera_image_api = { |
|
|
253
by Suren A. Chilingaryan
Provide version information as required by new pcilib interface |
206 |
IPECAMERA_VERSION, |
207 |
||
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
208 |
ipecamera_init, |
209 |
ipecamera_free, |
|
210 |
||
211 |
ipecamera_init_dma, |
|
212 |
||
213 |
ipecamera_reset, |
|
214 |
ipecamera_start, |
|
215 |
ipecamera_stop, |
|
216 |
ipecamera_trigger, |
|
217 |
||
218 |
ipecamera_stream, |
|
219 |
ipecamera_next_event, |
|
220 |
ipecamera_get, |
|
221 |
ipecamera_return
|
|
222 |
};
|
|
223 |
||
224 |
||
225 |
static const pcilib_model_description_t ipecamera_models[] = {{ |
|
226 |
PCILIB_EVENT_INTERFACE_VERSION, |
|
227 |
&ipecamera_image_api, |
|
228 |
&pcilib_ipedma, |
|
229 |
ipecamera_registers, |
|
230 |
ipecamera_banks, |
|
231 |
ipecamera_protocols, |
|
232 |
ipecamera_ranges, |
|
233 |
ipecamera_events, |
|
234 |
ipecamera_data_types, |
|
235 |
"ipecamera", |
|
236 |
"IPE Camera"
|
|
237 |
}, { 0 }}; |
|
238 |
||
239 |
||
240 |
const pcilib_model_description_t *pcilib_get_event_model(pcilib_t *pcilib, unsigned short vendor_id, unsigned short device_id, const char *model) { |
|
241 |
// Enumeration call
|
|
242 |
if ((!vendor_id)&&(!device_id)&&(!model)) { |
|
243 |
return ipecamera_models; |
|
244 |
}
|
|
245 |
||
|
247
by Suren A. Chilingaryan
Properly check for requested model |
246 |
if ((vendor_id != 0x10ee)||((model)&&(strcasecmp(model, "ipecamera")))) |
|
245
by Suren A. Chilingaryan
First stand-alone ipecamera implementation |
247 |
return NULL; |
248 |
||
249 |
return &ipecamera_models[0]; |
|
250 |
}
|